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oki semiconductor fedl674001-01 issue date: dec. 15, 2003 ml674001/q4002/q4003 32-bit arm-based general-purpose microcontroller arm, arm7tdmi, multi-ice and amba are re gistered trademarks of arm ltd., uk. plat is oki's trademark. the contents of this data sheet are subject to change for modification without notice. 1/24 general description the ml674001, ML67Q4002, and ml67q4003 microcontrollers (mcus) are the members of an extensive and growing family of 32-bit arm ? -based standard products for general-purpose applications that require 32-bit cpu performance and low cost afford ed by mcu integrated features. ml674001/67q4002/67q4003 provide built-in 32kbyte sram , built-in 4kbyte boot rom, and a host of other useful peripherals such as auto-reload timers, watchdog timer (wdt), pulse-width modulators (pwm), a-to-d converter, expanded uarts, synchronou s serial port, i2c serial interface, gpios, dma controller, external memory controller, and boundary scan capability. in addition, the ML67Q4002 and ml67q4003 offer 256 kbytes and 512 kbytes of built-in flash memory re spectively. the ml674001, ML67Q4002 and ml67q4003 are pin-to-pin compatib le with each other for easy performance updates. oki?s ml674k family mcus are capable of executing both the 32-bit arm instruction set for high-performance applications as well as the 16-bit thumb ? instruction set for high code-density, power-efficient applications. with an arm7tdmi ? core operating at 33 mh z maximum frequency, arm thumb? capabilities, and robust feature sets, the ml 674001 series mcus are suitable for an array of applications including high performan ce industrial controllers and instrume ntation, telecom, pc peripherals, security/surveillance, test equipment, and a variety of consumer electronics devices. the arm7tdmi ? advantage oki?s ml674k family of low-cost arm-based mcus offers system designers a bridge from 8- and 16-bit proprietary mcu architectures to ar m?s higher-performance, affordable, widely-accepted industry standard architecture and its industry-wide support infrastructure. the arm industry infrastructure offers the system developers many advantages includin g software compatibility, many ready- to-use software applications, large choices among hardware and software development tools. these arm-based advantages allow oki?s customers to better leverage engineering resources, lower development costs, minimize project risks, and reduce their product time to market. in addition, migration of a design with an oki standard mcu to an oki custom solution is easily facilitated with its award-wi nning uplat? product development architecture. features ? cpu 32-bit risc cpu (arm7tdmi) 32-bit instructions (arm instructions) and 16- bit instructions (thumb instructions) mixed general purpose registers : 31 x 32 bits built-in barrel shifter and multiplier (32 bit x 8 bit, modified booth?s algorithm) little endian built-in debug function ? internal memory ram 32kb (32-bit access) flash (16-bit access) ml674001 : rom-less version ML67Q4002 : 256kbytes ml67q4003 : 512kbytes
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 2/24 ? external memory controller rom (flash): 16 mbytes sram: 16 mbytes dram: 64 mbytes (sdram and edo-dram support) external io devices: 16 mbytes x 2 banks, 4 chip select pins wait control input signal for each bank independent programma ble wait settings for each bank ? interrupt controller 28 sources: 23 internals and 5 externals (irq: 4, fiq: 1) ? dma controller 2 channels: dual address mode, cycle steal and burst tranfer mode ? timer 1 channel: 16-bit auto reload for operating system 6 channels: 16-bit auto reload for application 1 channel: 16 bit watchdog timer ? serial interface 1 channel: uart 1 channel: uart with 16-byte fifo 1 channel: synchronous 1 channel: i2c (single master) ? parallel i/o port 4 ports x 8 bits (bitwise input/output settings) 1 port x 10 bit (bitwise input/output settings) ? pwm 2 channels x 16 bits ? analog-to-digital converter 4 channels x 10 bits ? power down mechanism standby (all clock stop) and halt (c lock stop by each function block) clock gear (selectable 1/1, 1/2, 1/4, 1/8, 1/16 input clock frequency) ? jtag interface connectable to jtag ice ? power supply voltage core section: 2.25 v to 2.75 v io section: 3.0 v to 3.6 v analog section: 3.0 v to 3.6 v ? operating frequency 1-33 mhz ? operating temperature (ambient temperature) ?40 c to +85 c ? package 144-pin plastic lqfp (lqfp144-p-2020-0.50) 144-pin plastic lfbga (p-lfbga144-1111-0.80)
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 3/24 block diagram tic internal & external memory controller irc a hb bridge arm7tdmi a pb bridge uart system control system tmr plat-7b cgb amba ahb bus amba apb bus tdi tdo ntrst tms tck 5 reset_n osc0 osc1_n vdd_core vdd_io gnd a vdd a gnd drame_n test bsel[1:0] fwr jsel pioe[8:5] / exint[3:0] pioe[9] / efiq_n 5 piob[6] / stxd piob[7] / srxd pioc[6:2] / xa[23:19] xa[18:0] xd[15:0] pioc[7] / xwr xoe_n xwe_n xbwe_n[1:0] xromcs_n xramcs_n xiocs_n[3:0] xbs_n[1:0] piod[0] / xwait piod[1] / xcas_n piod[2] / xras_n piod[3] / xsdclk piod[4] / xsdcs_n piod[5] / xsdcke piod[6] / xdqm[1]/xcas_n[1] piod[7] / xdqm[0]/xcas_n[0] dramc internal ram 32kb a pb bridge wdt uart (16550) pioa[0] / sin pioa[1] / sout pioa[2] / cts pioa[3] / dsr pioa[4] / dcd pioa[5] / dtr pioa[6] / rts pioa[7] / ri exp. irc apb bus tmr 16 bit x 6ch 8 a/d a in[3:0] vref 5 pwm 16 bit x 2ch 2 pioc[1:0] / pwmout[1:0] gpio 42 dmac pioa[7:0] piob[7:0] pioc[7:0] piod[7:0] pioe[9:0] piob[0] / dreq[0] piob[2] / dreq[1] piob[1] / dreqclr[0] piob [ 3 ] / dreqclr [ 1 ] piob[4] / tcout[0] piob[5] / tcout[1] 2 2 2 ssio pioe[0] / sclk pioe[1] / sdi pioe [ 2 ] / sdo 3 i2c pioe[3] / sd a pioe[4] / scl 2 internal (mcp) flash rom ML67Q4002 : 256kb ml67q4003 : 512kb boot rom 4kb ckoe_n cko
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 4/24 pin configuration (top view) 144-pin plastic lfbga 13121110987654321 n piod[6]/ xdqm[1 ] xiocs_ n[3] xiocs_ n[1] xramc s_n xbwe_ n[0] xoe_n pioc[4]/ xa[21] xa[16] xa[14] xa[11] xa[9] xa[7] xa[6] m piod[7]/ xdqm[0 ] xiocs_ n[2] xiocs_ n[0] xwe_n pioc[7]/ xwr pioc[6]/ xa[23] pioc[2]/ xa[19] xa[17] xa[15] xa[13] xa[10] xa[4] xa[5] l piob[1]/ dreqc lr[0] piob[2]/ dreq[1] piob[0]/ dreq[0] xromc s_n xbwe_ n[1] pioc[5]/ xa[22] pioc[3]/ xa[20] xa[18] xa[12] vdd_io xa[8] xa[2] gnd k piob[3]/ dreqc lr[1] piob[5]/ tcout[ 1] vdd_io gnd vdd_io vdd_c ore vdd_io gnd gnd xa[3] xa[0] xd[13] xa[1] j pioc[0]/ pwmou t[0] gnd piob[4]/ tcout[ 0] pioc[1]/ pwmou t[1] vdd_io xd[15] xd[11] xd[14] h xbs_n[ 0] xbs_n[ 1] piod[0]/ xwait vdd_c ore vdd_c ore xd[10] nc xd[12] g piod[2]/ xras_n piod[1]/ xcas_n vdd_io gnd vdd_io xd[8] nc xd[9] f bsel[1] piod[5]/ xsdck e piod[3]/ xsdclk piod[4]/ xsdcs_ n gnd xd[7] xd[6] xd[5] e pioe[7]/ exint[2] bsel[0] pioe[8]/ exint[3] pioe[5]/ exint[0] gnd xd[2] nc xd[4] d pioe[0]/ sclk pioe[6]/ exint[1] pioe[9]/ efiq_n pioe[2]/ sdo osc1_n pioa[1]/ sout ain[0] nc vdd_io gnd vdd_io xd[3] xd[1] c tdi pioe[1]/ sdi cko tms ckoe_ n avdd ain[1] ain[3] vdd_c ore pioa[5]/ dtr fwr xd[0] reset_ n b ntrst tdo tck gnd vdd_io pioa[0]/ sin vref agnd gnd pioa[3]/ dsr pioa[7]/ ri pioe[4]/ scl piob[7]/ srxd a nc nc jsel drame _n osc0 test ain[2] pioa[2]/ cts pioa[4]/ dcd pioa[6]/ rts pioe[3]/ sda piob[6]/ stxd nc 13121110987654321 144pin lfbga (top view) notes: nc pins are electrically unconnected in the package. nc pins can be connected to vdd or gnd.
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 5/24 144-pin plastic lqfp ( secondar y fu n ( primar y function ) 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ( primar y functi ( secondar y f nc 72 xiocs_n[3] nc 71 xiocs_n[2] cko 70 xiocs_n[1] jsel 69 gnd tms 68 xiocs_n[0] tck 67 xramcs_n drame_n 66 xromcs_n ckoe_n 65 xbwe_n[1] gnd 64 xbwe_n[0] osc0 63 xwe_n osc1_n 62 v dd_io v dd_io 61 xoe_n test 60 pioc[7] xwr sin pioa[0] 59 pioc[6] xa[23] sout pioa[1] 58 v dd_core avdd 57 pioc[5] xa[22] v ref 56 pioc[4] xa[21] ain[0] 55 pioc[3] xa[20] ain[1] 54 v dd_io ain[2] 53 pioc[2] xa[19] ain[3] 52 xa[18] nc 51 gnd agnd 50 xa[17] gnd 49 xa[16] cts pioa[2] 48 xa[15] v dd_io 47 gnd dsr pioa[3] 46 xa[14] dcd pioa[4] 45 xa[13] v dd_core 44 xa[12] dtr pioa[5] 43 xa[11] rts pioa[6] 42 xa[10] ri pioa[7] 41 v dd_io gnd 40 xa[9] sda pioe[3] 39 xa[8] scl pioe[4] 38 xa[7] stxd piob[6] 37 xa[6] 1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233343536 xdqm[0]/xcas_n[0] xdqm[1]/xcas_n[1] dreq[0] dreqclr[0] dreqclr[1] dreq[1] tdo ntrst tcout[1] pwmout[0] pwmout[1] xbs _ n[0] xbs _ n[1] pioe[0] pioe[1] pioe[2] tdi pioe[6] pioe[7] pioe[8] pioe[9] piod[5] bsel[0] bsel[1] pioe[5] piod[1] gnd vdd _ io piod[2] piob[5] pioc[0] piod[0] vdd _ core ( primar y f ( second a piob[0] piod[7] tcout[0] xwait pioc[1] gnd piob[3] piob[4] piod[6] piob[1] vdd _ io piob[2] xa[5] vdd _ io srxd xcas _ n xras _ n xsdclk xsdcs _ n xsdcke exint[0] xa[2] xa[3] gnd xa[4] xd[14] xd[15] xa[0] xa[1] xd[11] xd[12] vdd _ io xd[13] xd[9] xd[10] vdd _ cor e nc xd[7] nc xd[8] exint[1] nc xd[5] xd[6] gnd piod[3] piod[4] xd[2] xd[3] xd[4] gnd vdd _ io xd[0] xd[1] exint[2] exint[3] efiq _ n sclk sdi 102 101 nc piob[7] fwr reset _ n ( primar y f ( second a sdo 100 108 107 106 105 104 103 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 144pin lqfp (top view) notes: nc pins are electrically unconnected in the package. nc pins can be connected to vdd or gnd.
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 6/24 list of pins pin primary function secondary function lqfp bga symbol i/o description symbol i/o description 1 a1 nc ? nc ? ? 2 b1 piob[7] i/o general port (with interr upt function) srxd i sio receive signal 3 c3 fwr i test mode ? ? 4 c1 reset_n i reset input ? ? 5 d3 vdd_io vdd io power supply ? ? 6 c2 xd[0] i/o external data bus ? ? 7 d1 xd[1] i/o external data bus ? ? 8 e3 xd[2] i/o external data bus ? ? 9 d2 xd[3] i/o external data bus ? ? 10 e1 xd[4] i/o external data bus ? ? 11 e4 gnd gnd gnd ? ? 12 e2 nc ? nc ? ? 13 f1 xd[5] i/o external data bus ? ? 14 f2 xd[6] i/o external data bus ? ? 15 f4 gnd gnd gnd ? ? 16 f3 xd[7] i/o external data bus ? ? 17 g2 nc ? nc ? ? 18 g4 vdd_io vdd i/o power supply ? ? 19 g3 xd[8] i/o external data bus ? ? 20 g1 xd[9] i/o external data bus ? ? 21 h3 xd[10] i/o external data bus ? ? 22 h4 vdd_core vdd core power supply ? ? 23 h2 nc ? nc ? ? 24 j2 xd[11] i/o external data bus ? ? 25 h1 xd[12] i/o external data bus ? ? 26 j4 vdd_io vdd i/o power supply ? ? 27 k2 xd[13] i/o external data bus ? ? 28 j1 xd[14] i/o external data bus ? ? 29 j3 xd[15] i/o external data bus ? ? 30 k3 xa[0] o external address output ? ? 31 k1 xa[1] o external address output ? ? 32 l2 xa[2] o external address output ? ? 33 k4 xa[3] o external address output ? ? 34 l1 gnd gnd gnd ? ? 35 m2 xa[4] o external address output ? ? 36 m1 xa[5] o external address output ? ? 37 n1 xa[6] o external address output ? ? 38 n2 xa[7] o external address output ? ? 39 l3 xa[8] o external address output ? ? 40 n3 xa[9] o external address output ? ?
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 7/24 pin primary function secondary function lqfp bga symbol i/o description symbol i/o description 41 l4 vdd_io vdd i/o power supply ? ? 42 m3 xa[10] o external address output ? ? 43 n4 xa[11] o external address output ? ? 44 l5 xa[12] o external address output ? ? 45 m4 xa[13] o external address output ? ? 46 n5 xa[14] o external address output ? ? 47 k5 gnd gnd gnd ? ? 48 m5 xa[15] o external address output ? ? 49 n6 xa[16] o external address output ? ? 50 m6 xa[17] o external address output ? ? 51 k6 gnd gnd gnd ? ? 52 l6 xa[18] o external address output ? ? 53 m7 pioc[2] i/o general port (with interrupt function) xa[19] o external address output 54 k7 vdd_io vdd i/o power supply ? ? 55 l7 pioc[3] i/o general port (with interrupt function) xa[20] o external address output 56 n7 pioc[4] i/o general port (with interrupt function) xa[21] o external address output 57 l8 pioc[5] i/o general port (with interrupt function) xa[22] o external address output 58 k8 vdd_core vdd core power supply ? ? 59 m8 pioc[6] i/o general port (with interrupt function) xa[23] o external address output 60 m9 pioc[7] i/o general port (with interr upt function) xwr o transfer direction of external bus 61 n8 xoe_n o output enable (excluding sdram) ? ? 62 k9 vdd_io vdd i/o power supply ? ? 63 m10 xwe_n o write enable ? ? 64 n9 xbwe_n[0] o byte write enable (lsb) ? ? 65 l9 xbwe_n[1] o byte write enable (msb) ? ? 66 l10 xromcs_n o external rom chip select ? ? 67 n10 xramcs_n o external ram chip select ? ? 68 m11 xiocs_n[0] o io chip select 0 ? ? 69 k10 gnd gnd gnd ? ? 70 n11 xiocs_n[1] o io chip select 1 ? ? 71 m12 xiocs_n[2] o io chip select 2 ? ? 72 n12 xiocs_n[3] o io chip select 3 ? ? 73 n13 piod[6] i/o general port (with interrupt function) xdqm[1]/xcas _n[1] o input/output mask/cas (msb) 74 m13 piod[7] i/o general port (with interrupt function) xdqm[0]/xcas _n[0] o input/output mask/cas (lsb) 75 l11 piob[0] i/o general port (with interrupt function) dreq[0] i dma request signal (ch0) 76 l13 piob[1] i/o general port (with interrupt function) dreqclr[0 ] o dreq clear signal (ch0) 77 k11 vdd_io vdd i/o power supply ? ? 78 l12 piob[2] i/o general port (with interr upt function) dreq[1] i dma request signal (ch1)
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 8/24 pin primary function secondary function lqfp bga symbol i/o description symbol i/o description 79 k13 piob[3] i/o general port (with interr upt function) dreqclr[1 ] o dreq clear signal (ch1) 80 j11 piob[4] i/o general port (with interrupt function) tcout[0] o dmac terminal count (ch0) 81 k12 piob[5] i/o general port (with interrupt function) tcout[1] o dmac terminal count (ch1) 82 j13 pioc[0] i/o general port (with interr upt function) pwmout[0] o pwm output (ch0) 83 j10 pioc[1] i/o general port (with interr upt function) pwmout[1] o pwm output (ch1) 84 j12 gnd gnd gnd ? ? 85 h13 xbs_n[0] o external bus byte select (lsb) ? ? 86 h12 xbs_n[1] o external bus byte select (msb) ? ? 87 h10 vdd_core vdd core power supply ? ? 88 h11 piod[0] i/o general port (with interrupt function) xwait i wait input signal for i/o banks 89 g12 piod[1] i/o general port (with interr upt function) xcas_n o column address strobe (sdram) 90 g10 gnd gnd gnd ? ? 91 g11 vdd_io vdd i/o power supply ? ? 92 g13 piod[2] i/o general port (with inte rrupt function) xras_n o row address strobe (sdram/edo) 93 f11 piod[3] i/o general port (with interrupt function) xsdclk o clock for sdram 94 f10 piod[4] i/o general port (with interrupt function) xsdcs_n o chip select for sdram 95 f12 piod[5] i/o general port (with interr upt function) xsdcke o clock enable (sdram) 96 e12 bsel[0] i select boot device ? ? 97 f13 bsel[1] i select boot device ? ? 98 e10 pioe[5] i/o general port (with interr upt function) exint[0] i interrupt input 99 d12 pioe[6] i/o general port (with interr upt function) exint[1] i interrupt input 100 e13 pioe[7] i/o general port (with interr upt function) exint[2] i interrupt input 101 e11 pioe[8] i/o general port (with interr upt function) exint[3] i interrupt input 102 d11 pioe[9] i/o general port (with in terrupt function) efiq_n i fiq input 103 d13 pioe[0] i/o general port (with in terrupt function) sclk i/o ssio clock 104 c12 pioe[1] i/o general port (with interrupt function) sdi i ssio serial data in 105 d10 pioe[2] i/o general port (with interrupt func tion) sdo o ssio serial data out 106 c13 tdi i jtag data input ? ? 107 b12 tdo o jtag data out ? ? 108 b13 ntrst i jtag reset ? ? 109 a13 nc ? nc ? ? 110 a12 nc ? nc ? ? 111 c11 cko o clock output ? ? 112 a11 jsel i jtag select ? ? 113 c10 tms i jtag mode select ? ? 114 b11 tck i jtag clock ? ? 115 a10 drame_n i dram enable ? ?
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 9/24 pin primary function secondary function lqfp bga symbol i/o description symbol i/o description 116 c9 ckoe_n i clock out enable ? ? 117 b10 gnd gnd gnd ? ? 118 a9 osc0 i oscillation input pin ? ? 119 d9 osc1_n o oscillation output pin ? ? 120 b9 vdd_io vdd io power supply ? ? 121 a8 test i test mode input ? ? 122 b8 pioa[0] i/o general port (with interrupt function) sin i uart serial data in 123 d8 pioa[1] i/o general port (with interrupt function) sout o uart serial data out 124 c8 avdd vdd a/d converter power supply ? ? 125 b7 vref i a/d converter reference voltage ? ? 126 d7 ain[0] i a/d converter analog input port ? ? 127 c7 ain[1] i a/d converter analog input port ? ? 128 a7 ain[2] i a/d converter analog input port ? ? 129 c6 ain[3] i a/d converter analog input port ? ? 130 d6 nc ? nc ? ? 131 b6 agnd gnd gnd for a/d converter ? ? 132 b5 gnd gnd gnd ? ? 133 a6 pioa[2] i/o general port (with interr upt function) cts i uart clear to send 134 d5 vdd_io vdd io power supply ? ? 135 b4 pioa[3] i/o general port (with interrupt function) dsr i uart set ready 136 a5 pioa[4] i/o general port (with interr upt function) dcd i uart carrier detect 137 c5 vdd_core vdd core power supply ? ? 138 c4 pioa[5] i/o general port (with interr upt function) dtr o uart data terminal ready 139 a4 pioa[6] i/o general port (with interr upt function) rts o uart request to send 140 b3 pioa[7] i/o general port (with interr upt function) ri i uart ring indicator 141 d4 gnd gnd gnd ? ? 142 a3 pioe[3] i/o general port (with interrupt f unction) sda i/o i2c data in/out 143 b2 pioe[4] i/o general port (with interrupt function) scl o i2c clock out 144 a2 piob[6] i/o general port (with interrupt function) stxd o sio send data output
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 10/24 pin description pin name i/o description primary/ secondary logic system reset_n i reset input ? negative bsel[1:0] i boot device select signal bsel[1] bsel[0] boot device 0 0 internal flash (external rom for ml674001) 0 1 external rom 1 * boot mode the selected device is mapped to bank0 (0x0000_0000 - 0x07ff_ffff) after reset. ? positive osc0 i crystal connection or external clock input. connect a crystal (16 mhz to 33 mhz), if used, to osc0 and osc1_n. it is also possible to input a direct clock. ? ? osc1_n o crystal connection. when not using a crystal, leave this pin unconnected. ? ? cko o clock out ? ? ckoe_n i clock out enable ? negative debugging support. tck i debugging pin. normally connect to ground level. ? ? tms i debugging pin. normally drive at high level. ? positive ntrst i debugging pin. normally connect to ground level. ? negative tdi i debugging pin. normally drive at high level. ? positive tdo o debugging pin. normally leave open. ? positive general-purpose i/o ports pioa[7:0] i/o general-purpose port. not available for use as port pins when secondary functions are in use. primary positive piob[7:0] i/o general-purpose port. not available for use as port pins when secondary functions are in use. primary positive pioc[7:0] i/o general-purpose port. not available for use as port pins when secondary functions are in use. primary positive piod[7:0] i/o general-purpose port. not available for use as port pins w hen secondary functions are in use. note that enabling dram controller with drame_n inputs permanently configures piod[7:0] for their secondary functions, making them unavailable for use as port pins. primary positive pioe[9:0] i/o general-purpose port. not available for use as port pins when secondary functions are in use. primary positive
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 11/24 pin name i/o description primary / secondary logic external bus xa[23:19] o address bus to external ram, external rom, external i/o banks, and external dram. after a reset, these pi ns are configured for their primary function (pioc[6:2]). secondary positive xa[18:0] o address bus to external ram, external rom, external i/o banks, and external dram. ? positive xd[15:0] i/o data bus to external ram, ex ternal rom, external i/o banks, and external dram. ? positive external bus control signals (rom/sram/io) xromcs_n o rom bank chip select ? negative xramcs_n o sram bank chip select ? negative xiocs_n[0] o io chip select 0 ? negative xiocs_n[1] o io chip select 1 ? negative xiocs_n[2] o io chip select 2 ? negative xiocs_n[3] o io chip select 3 ? negative xoe_n o output enable/ read enable ? negative xwe_n o write enable ? negative xbs_n[1:0] o byte select: xbs_n[1] is for msb, xbs_n[0] is for lsb ? negative xbwe_n[0] o lsb write enable ? negative xbwe_n[1] o msb write enable ? negative xwr o data transfer direction for exter nal bus, used when connecting to motorola i/o devices. this represent the secondary function of pin pioc[7]. l: read , h: write. available for i/o bank 0/1. secondary ? xwait i external i/o bank 0/1, 2/3 wait signal. this input permits access to devic es slower than register settings. secondary positive external bus control signals (dram) xras_n o row address strobe. used for both edo dram and sdram secondary negative xcas_n o column address strobe signal (sdram) secondary negative xsdclk o sdram clock (same frequency as internal hclk) secondary ? xsdcke o clock enable (sdram) secondary ? xsdcs_n o chip select (sdram) secondary negative xdqm[1]/xcas_n[1] o connected to sdram: dqm (msb) connected to edo dram: column address strobe signal (msb) secondary positive/ negative xdqm[0]/xcas_n[0] o connected to sdram: dqm (lsb) connected to edo dram: column address strobe signal (lsb) secondary positive/ negative
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 12/24 pin name i/o description primary / secondary logic dma control signals dreq[0] i ch 0 dma request signal, us ed when dma controller configured for dreq type secondary positive dreqclr[0] o ch 0 dreq signal clear r equest. the dma device responds to this output by negating dreq. secondary positive tcout[0] o indicates to ch 0 dma device that last transfer has started. secondary positive dreq[1] i ch 1 dma request signal, us ed when dma controller configured for dreq type secondary positive dreqclr[1] o ch 1 dreq signal clear r equest. the dma device responds to this output by negating dreq. secondary positive tcout[1] o indicates to ch 1 dma device that last transfer has started secondary positive uart sin i sio receive signal secondary positive sout o sio transmit signal secondary positive cts i clear to send. indicates that modem or data set is ready to transfer data. bit 4 in modem status register reflects this input. secondary negative dsr i data set ready. indicates that modem or data set is ready to establish a communications link with uart. bit 5 in modem status regi ster reflects this input. secondary negative dcd i data carrier detect. indicates that modem or data set has detected data carrier signal. bit 7 in modem status register reflects this input. data carrier detect secondary negative dtr o data terminal ready. indicates that uart is ready to establish a communications link with modem or data set. bit 0 in modem control register controls this output. secondary negative rts o request to send. indicates that uart is ready to transfer data to modem or data set. bit 1 in modem control register controls this output. secondary negative ri i ring indicator. indicates that modem or data set has received telephone ring indicator. bit 6 in modem status register reflects this input. secondary negative
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 13/24 pin name i/o description primary / secondary logic sio stxd o sio transmit signal secondary positive srxd i sio receive signal secondary positive i2c sda i/o i2c data. this pin operates as nmos open drain. connect pull-up resistor. secondary positive scl o i2c clock. this pin operates as nmos open drain. connect pull-up resistor. secondary ? synchronous sio sclk i/o serial clock secondary ? sdi i serial receive data secondary positive sdo o serial transmit data secondary positive pwm signals pwmout[0] o pwm output of ch0 secondary positive pwmout[1] o pwm output of ch1 secondary positive analog-to-digital converter ain[0] i ch0 analog input ? ? ain[1] i ch1 analog input ? ? ain[2] i ch2 analog input ? ? ain[3] i ch3 analog input ? ? vref i analog-to-digital conver ter convert reference voltage ? ? avdd analog-to-digital c onverter power supply ? ? agnd analog-to-digital converter ground ? ? interrupt signals exint[3:0] i external interrupt input signals. secondary positive / negative efiq_n i external fast interrupt input signal. interrupt controller connects this to cpu fiq input. secondary negative mode configuration drame_n i dram enable mode ? negative test i test mode ? positive fwr i test mode ? positive jsel i jtag select signal. l: on-board debug, h: boundary scan. ? ? power supplies vdd_core core power supply ? ? vdd_io i/o power supply ? ? gnd gnd for core and i/o ? ?
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 14/24 description of functions cpu cpu core: arm7tdmi operating frequency: 1 mhz to 33 mhz byte ordering: little endian instructions: arm instruction (32-bit length) and thumb instruction (16-bit length) can be mixed. general register bank: 31 32 bits built-in barrel shifter: alu and barrel shift operations can be executed by one instruction. multiplier: 32 bits 8 bits (modified booth?s algorithm) built-in debug function: jtag inte rface, break point register built-in memory flash rom: ml674001 : rom-less version ML67Q4002 : 256kbytes (128k x 16 bits) ml67q4003 : 512kbytes (256k x 16 bits) access timing of this flash memory is conf igured by the rom bank control register of the external memory controller. ram: 32kb (8k x 32bits) read access(8/16/32bit): 1 cycle, write access(32bit): 1 cycle, write aceess(8/16bit): 2 cycle, interrupt controller fast interrupt request (fiq) and interrupt request (irq) are employed as interrupt in put signals. the interrupt controller controls these interrupt signals going to arm core. (1) interrupt sources fiq: 1 external source (external pin: efiq_n) irq: total of 27 sources. 23 internal sources, and 4 external sources (external pins: exint[3:0]) (2) interrupt priority level configurable, 8-level priority for each source (3) external interrupt pin input exint[3:0] can be set as level or edge sensing. configurable high or low when level sensing. configurable rise or falling edge triggering when edge sensing. efiq_n is set as falling edge triggering. timers 7 channels of 16-bit reload timers are employed. of th ese, 1 channel is used as system timer for os. the timers of other 6 channels are used in application software. (1) system timer: 1 channel 16-bit auto reload timer: used as system timer for os. interrupt request by timer overflow. (2) application timer: 6 channels 16-bit auto reload timer. interrupt request by compare match. one shot, interval clock can be independently set for each channel
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 15/24 wdt functions as an interval timer or a watch dog timer. (1) 16-bit timer (2) watch dog timer or interval timer mode can be selected (3) interrupt or reset generation. (4) maximum period: longer than 200 msec pwm this lsi contains two channels of pwm (pulse width modulation) function which can change the duty cycle of a waveform with a constant period. the pwm output resolution is 16 bits for each channel. serial interface this lsi contains four serial interface. (1) uart without fifo : 1 channel this is the serial port which performs data transmission, taking a synchronization per character. selection of various parameters, such as addition of da ta length, a stop bit, and a parity bit, is possible. - asynchronous full duplex operation - sampling rate = baud rate x 16sample - character length : 7, 8 bit - stop bit length : 1, 2 bit - parity : even, odd, none - error detection : parity, framing, over run - loop back function : on/off, parity, framing, over run compulsive addition - baud rate generation : exclusive baud rate generator built-in (8bit counter) independent from a bus clock - internal-baud-rate-clock-stop at the time of halt mode. (2) uart with 16bytes fifo : 1channel features 16bytes fifo in both send and recei ve. uses the industry standard 16550a ace (asynchronous communication element). - asynchronous full duplex operation - reporting function for all status - 16 byte transmission and reception fifo - transmission, reception, interr upt of line status data set a nd independent fifo control. - modem control signals : cts, dcd, dsr, dtr, ri and rts - data length : 5, 6, 7, 8 bit - stop bit length : 1, 1.5, 2 bit - parity : even, odd, none - error detection : parity, framing, overrun - baud rate generation : exclusive baud rate generator built-in (3) synchronous serial interface : 1channel it is a clock synchronous 8bit serial port - selectable 1/8, 1/16 or 1/32 of hclk frequency. - choose lsb first or msb first. - choose master / slave mode - transceiver interruption, transceiver buffer empty interrupt - loopback test function (4) i2c : 1channel based on the i2c bus specifications. op erates as a single master device. - communication mode : master transmitter /master receiver - transmission speed : 100kbps (standard mode) / 400kbps (fast mode) - addressing format : 7 bit / 10 bit - data buffer : 1 byte(1step) - communication voltage : 2.7v to 3.3v
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 16/24 gpio 42-bits parallel port (four 8-bit ports and one 10-bit port) . pioa[7:0] combination port uart piob[7:0] combination port dmac, uart(uplat-7b), pioc[7:0] combination port pwm, xa[23:19], xwr piod[7:0] combination port dram contorol signal etc. pioe[9:0] combination port ssio, i2c, external interrupt signal (1) input/output selectable at bit level. (2) each bit can be used as an interrupt source. (3) interrupt mask and interrupt polarity can be set for all bits. (4) the ports are configured as input, immediately after reset. (5) primary/secondary function of each port can be set independently. ad converter successive approximation type ad converter. (1) 10 bits 4 channels (2) sample hold function (3) scan mode and select mode are supported (4) interrupt is generated after completion of conversion. (5) conversion time: 5 s minimum. dmac two channels of direct memory access controller which transfers data between memory and memory, between i/o and memory and between i/o and i/o. (1) number of channels: 2 channels (2) channel priority level: fixed mode channel priority level is always fixed (channel 0 > 1). roundrobin priority level of the channel requested for transfer is kept lowest. (3) maximum number of transfers: 65,536 times (64k times) (4) data transfer size: byte (8 bits), half-word (16 bits), word (32 bits) (5) bus request system: cycle steal mode bus request signal is asserted for each dma transfer cycle. burst mode bus request signal is asserted until all transfers of transfer cycles are complete. (6) dma transfer request: software request by setting the software transfer requ est bit inside dmac, the cpu starts dma transfer. external request dma transfer is started by extern al request allocated to each channel. (7) interrupt request: interrupt request is generated to cpu after the end of dma transfers for the set number of transfer cycles or after occurrence of error. interrupt request signal is out put separately for each channel. interrupt request si gnal output can be masked for each channel.
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 17/24 external memory controller controls access of externally connected devices su ch as rom (flash), sram, sdram (edo dram), io devices, and internal flash memory. (1) rom (flash) access function : 1 bank supports 16-bit devices. supports flash memory: byte write (can be written only by if e quivalent to sram). in ML67Q4002/ml67q4003, control internal flash access. configurable access timing. (2) sram access function : 1 bank supports 16-bit devices. supports asynchronous sram configurable access timing. (3) dram access function : 1 bank supports 16-bit device supports edo/sdram : simultaneous connections to edo-dram and sdram cannot be made. configurable access timing. (4) external io access function : 2 banks supports 8-bit/16-bit access : indepe ndent configuration for each bank each bank has two chip selects : xiocs_n[3:0] supports external wait input : xwait access timing configurable for each bank independently power management halt, standby, clock gear, clock control func tions are supported as power save functions. (1) halt mode halt object cpu, internal ram, ahb bus control halt mode setting: set by the system control register. exit halt mode due to: reset, interrupt (2) standby mode stops the clock of entire lsi. standby mode setting: specified by the system control register. exit standby mode due to: reset, external interrupt (other than efiq_n) (3) clock gear this lsi has two clock systems, hclk and cclk. configure hclk and cclk frequency. hclk: cpu, bus control, sync hronous serial interface, i2c. cclk: timers, pwm, uart, ad converter, etc. (4) clock control by each function unit ad converter, pwm, timers, dramc, dmac, uart(fifo), uart, synchronous sio, i2c.
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 18/24 built-in flash rom programming the robust features of the flash permit simple and optimized programming as well as maintaining the flash-rom. (1) programming method ? programming via jtag interface ? programming using boot mode boot mode of this lsi is used for downloading data to be written to the flash through the uart interface of the mcu from a host system. in boot mode, the program on the on-chip boot rom downloads a flash writing application, that will handle th e serial transfer and writing of internal flash, to internal ram area of the mcu thr ough the uart interface of the mcu. ? programming via user application running from external memory internal flash can be programmed by executing a user flash progr amming application from external memory. (2) single power source for read/program of flash: 3.0v to 3.6v (3) programming units : 2 bytes (4) selectable erasing size ? sector erase: 2kbytes/sector ? block erase: 64kbytes/block ? chip erase: all memory cell (5) word program time: 30usec (6) sector/block erase time: 25msec (7) chip erase time: 100msec (8) write protection ? block protect: top address 8kwords can be protected ? chip protect: all words can be protected (9) number of commands: 9 (10) highly reliable read/program ? sector programming: 1000 times ? data hold period: 10 years
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 19/24 absolute maximum ratings *1 item symbol conditions rating unit digital power supply voltage (core) v dd_core ?0.3 to +3.6 digital power supply voltage (i/o) v dd_io ?0.3 to +4.6 input voltage v i ?0.3 to v dd_io +0.3 output voltage v o ?0.3 to v dd_io +0.3 analog power supply voltage av dd ?0.3 to v dd_io +0.3 analog reference voltage v ref ?0.3 to v dd_io +0.3 and ?0.3 to av dd +0.3 analog input voltage v ai ?0.3 to v ref v input current i i ?10 to +10 output current * 2 ?20 to +20 output current * 3 i o gnd = agnd = 0 v ta = 25 c ?30 to +30 ma power losses (lfbga) 680 power losses (lqfp) p d ta = 85 c per package 1000 mw storage temperature t stg ? ?50 to +150 c note 1. these are maximum ratings not for general operation. exceeding these maximum ratings could cause damage or lead to permanent deterioration of the device. 2. all output pins except xa[15:0] 3. xa[15:0] operating conditions (gnd = 0 v) item symbol conditions minimum typical maximum unit digital power supply voltage (core) v dd_core 2.25 2.5 2.75 digital power supply voltage (i/o) v dd_io v dd_io v dd_core 3.0 3.3 3.6 analog power supply voltage av dd a vdd = v dd_io 3.0 3.3 3.6 analog reference voltage v ref v ref = a vdd = v dd_io 3.0 3.3 3.6 v operating frequency * f op v dd_core = 2.25 to 2.75 v dd_io = 3.0 to 3.6 1 ? 33.333 mhz ambient temperature ta ? ?40 25 +85 c note operating frequencies between 16 mhz and 33 mhz. minimum of 2.56 mhz for external sdram. minimum of 6.4 mhz for external edo dram. mi nimum of 2 mhz for analog-to-digital converter.
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 20/24 electrical characteristics dc characteristics (v dd_core = 2.25 to 2.75v, v dd_io = 3.0 to 3.6v, ta = ?40 to +85 c) item symbol conditions minimum typical maximum unit high level input voltage v ih v dd_io x0.8 ? v dd_io +0.3 low level input voltage v il ?0.3 ? v dd_io x0.2 v t+ ? 1.6 2.1 v t ? 0.7 1.1 ? schmitt input buffer threshold voltage v hys ? 0.4 0.5 ? i oh = ?100 a v dd ?0.2 ? ? high level output voltage v oh i oh = ?4 ma 2.35 ? ? low level output voltage i ol = 100 a ? ? 0.2 low level output voltage * 1 i ol = 4 ma ? ? 0.45 low level output voltage * 2 v ol i ol = 6 ma ? ? 0.45 v input leak current * 3 i ih /i il v i = 0 v/v dd_io ?50 ? 50 input leak current * 4 i il v i = 0 v pull-up resistance of 50 k ? ?200 ?66 ?10 input leak current * 5 i i v i = av dd / 0 v ?5 ? 5 output leak current i lo v o = 0 v/v dd_io ?50 ? 50 a input pin capacitance c i ? ? 6 ? output pin capacitance c o ? ? 9 ? i/o pin capacitance c io ? ? 10 ? pf analog-to-digital converter operative * 6 ? 320 650 analog reference power supply current i ref analog-to-digital converter stopped ? 1 2 i dds_core ? 20 100 current consumption (standby) i dds_io ta = 25 c * 7 ? 5 20 a i ddh_core ? 20 40 current consumption (halt) * 8 i ddh_io ? 5 10 i dd_core ? 40 70 current consumption (run) * 9 i dd_io f op = 33 mhz c l = 30 pf ? 18 30 ma notes 1. all output pins except xa[15:0] 2. xa[15:0] 3. all input pins except reset_n 4. reset_n pin, with 50 k ? pull-up resistance 5. analog input pins (ain0 to ain3) 6. analog-digital converter operation ratio is 20% 7. v dd_io or 0 v for input ports; no load for other pins 8. dram controller blocks stopped by drame_n pin setting 9. external rom used
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 21/24 analog-to-digital converter characteristics (v dd_core = 2.50 v, v dd_io = 3.3 v, ta = 25 c) item symbol conditions minimum typical maximum unit resolution n ? ? ? 10 bit linearity error e l ? 3 ? differential linearity error e d ? 3 ? zero scale error e zs ? 3 ? full scale error e fs analog input source impedance ri 1k ? ? 3 ? lsb conversion time t conv ? 5 ? ? s throughput ? 10 ? 200 khz notes: vdd_io and avdd should be supplied separately ? definition of terms (1) resolution: minimum input analog value recognized. for 10-bit resolution, this is (v ref ? aground) 1024. (2) linearity error: difference between the th eoretical and actual conversion characteristics. (note that it does not include quantization error.) the theoreti cal conversion characteristic divides the voltage range between v ref and agnd into 1024 equal steps. (3) differential linearity error: difference betw een the theoretical and actual input voltage change producing a 1-bit change in the digital output anywhere within the conversion range. this is an indicator of conversion character istic smoothness. the theoretical value is (v ref ? aground) 1024. (4) zero scale error: difference between the th eoretical and actual conversion characteristics at the point where the digital output switches from ?0x000? to ?0x001.? (5) full scale error: difference between the theo retical and actual conver sion characteristics at the point where the digital output switches from ?0x3fe? to ?0x3ff.?
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 22/24 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respon sible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 23/24 revision history page document no. date previous edition current edition description pedl674001-01 jan.15, 2003 ? ? preliminary edition 1 pedl674001-02 feb.17, 2003 3 3 preliminary edition 2 modified piob[4:5] assignment of bloc diagram fedl674001-01 dec. 15, 2003 ? ? final edition 1
fedl674001-01 oki semiconductor ml674001/67q4002/67q4003 24/24 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external cond itions are reflected in the actual circ uit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to , traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2003 oki electric industry co., ltd.

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